The present invention relates to a semiconductor structure for integrated injection logic (I.sup.2 L). More particularly, the invention relates to I.sup.2 L transistor structure and a method of making such transistor structure.
Integrated injection logic (I.sup.2 L) has been known in the art for over ten years. Solid state circuits formed of bipolar transistors using I.sup.2 L technology have the advantage of high speed, low power and high device packing density. This high packing density is achieved with the elimination of isolation by using transistors with a common emitter at the bottom of the devices. I.sup.2 L on silicon is now widely used for VLSI applications.
The switching speed of silicon devices is limited by the long minority carrier lifetime in silicon and the low emitter efficiency resulting from the doping profile. The carrier lifetime in group III-V compound semiconductors is usually shorter, however, and the emitter efficiency can be improved, irrespective of the doping profile, by use of heterojunction emitters; i.e., by emitters formed by PN junctions between different materials. Therefore, III-V compound semiconductors are ideal materials for implementing I.sup.2 L. III-V compound semiconductors have the further advantage of providing high mobility for charge carriers and permitting the formation of graded bandgaps to reduce the transit time. Therefore, I.sup.2 L on III-V compound semiconductors is a promising technology for high speed VLSI.
The fabrication of I.sup.2 L circuits on III-V compound semiconductors is hindered, however, by the difficulty in preparing a lateral transistor. The minority carrier diffusion length in a III-V compound semiconductor is very short (less than one micron). Since the base width in the lateral transistor must be smaller than this diffusion length, the definition of the base of a lateral transistor by lithography (diffusion) is nearly impractical.
The use of III-V compound semiconductors in the fabrication of I.sup.2 L also results in difficulty in making ohmic contact to the various layers which are buried in the structure. Since the different layers in the I.sup.2 L structure must be very thin to achieve high speed, it becomes difficult to achieve controlled ohmic contact to selected ones of these layers.
The German Patent Document "Offenlegungsschrift" No. 2,509,530 discloses various types of I.sup.2 L transistor structure. FIGS. 10A and 10B of this patent publication disclose a vertical, or so-called "inverted" transistor formed with a Schottky collector. The use of the Schottky (metal-to-semiconductor) junction is said to eliminate an extra collector doping step.
The British Pat. No. 1,528,029 discloses an I.sup.2 L semiconductor device formed of a lateral PNP transistor and a vertical NPN transistor. The injector region and the base region of the lateral PNP transistor are formed by double diffusion to enable the base region to have a substantially uniform, but narrow width. As mentioned above, however, the base foration in the lateral device by diffusion in a III-V compound semiconductor is impractical because the base width must be substantially less than one micron.